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is61lv6432 integrated silicon solution, inc. 1 preliminary sr018-1c 06/01/98 issi this document contains preliminary data. issi reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. we assume no responsibility for any errors which may appear in this publication. ? copyright 1997, integrated silicon solution , inc. features ? internal self-timed write cycle ? individual byte write control and global write ? clock controlled, registered address, data and control ? pentium? or linear burst sequence control using mode input ? three chip enables for simple depth expansion and address pipelining ? common data inputs and data outputs ? power-down control by zz input ? jedec 100-pin tqfp and pqfp package ? 3.3v v cc and 2.5v v ccq for 2.5 i/o's ? two clock enables and one clock disable to eliminate multiple bank bus contention. ? control pins mode upon power-up: C mode in interleave burst mode C zz in normal operation mode these control pins can be connected to gnd q or v ccq to alter their power-up state ? industrial temperature available description the issi is61lv6432 is a high-speed, low-power synchro- nous static ram designed to provide a burstable, high- performance, secondary cache for the pentium?, 680x0?, and powerpc? microprocessors. it is organized as 65,536 words by 32 bits, fabricated with issi 's advanced cmos technology. the device integrates a 2-bit burst counter, high- speed sram core, and high-drive capability outputs into a single monolithic circuit. all synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input. write cycles are internally self-timed and are initiated by the rising edge of the clock input. write cycles can be from one to four bytes wide as controlled by the write control inputs. separate byte enables allow individual bytes to be written. bw1 controls dq1-dq8, bw2 controls dq9-dq16, bw3 controls dq17-dq24, bw4 controls dq25-dq32, conditioned by bwe being low. a low on gw input would cause all bytes to be written. bursts can be initiated with either adsp (address status processor) or adsc (address status cache controller) input pins. subsequent burst addresses can be generated inter- nally by the is61lv6432 and controlled by the adv (burst address advance) input pin. asynchronous signals include output enable ( oe ), sleep mode input (zz), clock (clk) and burst mode input (mode). a high input on the zz pin puts the sram in the power-down state. when zz is pulled low (or no connect), the sram normally operates after three cycles of the wake-up period. a low input, i.e., gnd q , on mode pin selects linear burst. a v ccq (or no connect) on mode pin selects interleaved burst. is61lv6432 64k x 32 synchronous pipeline static ram may 1998 fast access time symbol parameter -166 -133 -117 -5 -6 -7 -8 unit t kq clk access time 5 5 55678 ns t kc cycle time 6 7.5 8.5 10 12 13 15 ns frequency 166 133 117 100 83 75 66 mhz issi
is61lv6432 2 integrated silicon solution, inc. preliminary sr018-1c 06/01/98 issi block diagram 16 binary counter a15-a0 bw1 gw clr ce clk q0 q1 mode a0' a0 a1 a1' clk adv adsc adsp 14 16 address register ce d clk q dq32-dq25 byte write registers d clk q dq24-dq17 byte write registers d clk q dq16-dq9 byte write registers d clk q dq8-dq1 byte write registers d clk q enable register ce d clk q enable delay register d clk q bwe bw4 ce1 ce3 ce2 bw2 bw3 64k x 32 memory array 32 input registers clk output registers clk 32 oe 4 32 oe data[32:1]
is61lv6432 integrated silicon solution, inc. 3 preliminary sr018-1c 06/01/98 issi pin configuration 100-pin tqfp and pqfp (top view) nc dq16 dq15 vccq gndq dq14 dq13 dq12 dq11 gndq vccq dq10 dq9 gnd nc vcc zz dq8 dq7 vccq gndq dq6 dq5 dq4 dq3 gndq vccq dq2 dq1 nc a6 a7 ce1 ce2 bw4 bw3 bw2 bw1 ce3 vcc gnd clk gw bwe oe adsc adsp adv a8 a9 nc dq17 dq18 vccq gndq dq19 dq20 dq21 dq22 gndq vccq dq23 dq24 vccq vcc nc gnd dq25 dq26 vccq gndq dq27 dq28 dq29 dq30 gndq vccq dq31 dq32 nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 mode a5 a4 a3 a2 a1 a0 nc nc gnd vcc nc nc a10 a11 a12 a13 a14 a15 nc 46 47 48 49 50 pin descriptions a0-a15 address inputs clk clock adsp processor address status adsc controller address status adv burst address advance bw1 - bw4 synchronous byte write enable bwe byte write enable gw global write enable ce1 , ce2, ce3 synchronous chip enable oe output enable dq1-dq32 data input/output zz sleep mode mode burst sequence mode v cc +3.3v power supply gnd ground v ccq isolated output buffer supply: +3.3v gnd q isolated output buffer ground nc no connect
is61lv6432 4 integrated silicon solution, inc. preliminary sr018-1c 06/01/98 issi truth table address operation used ce1 ce1 ce1 ce1 ce1 ce2 ce3 ce3 ce3 ce3 ce3 adsp adsp adsp adsp adsp adsc adsc adsc adsc adsc adv adv adv adv adv write write write write write oe oe oe oe oe dq deselected, power-down none h x x x l x x x high-z deselected, power-down none l l x l xxxx high-z deselected, power-down none l x h l xxxx high-z deselected, power-down none l l x h l x x x high-z deselected, power-down none l x h h l x x x high-z read cycle, begin burst external l h l l x x x l q read cycle, begin burst external l h l l x x x h high-z write cycle, begin burst external l h l h l x l x d read cycle, begin burst external l h l h l x h l q read cycle, begin burst external l h l h l x h h high-z read cycle, continue burst next x x x h h l h l q read cycle, continue burst next x x x h h l h h high-z read cycle, continue burst next h x x x h l h l q read cycle, continue burst next h x x x h l h h high-z write cycle, continue burst next x x x h h l l x d write cycle, continue burst next h x x x h l l x d read cycle, suspend burst current x x x hhhhlq read cycle, suspend burst current x x x hhhhh high-z read cycle, suspend burst current h x x x h h h l q read cycle, suspend burst current h x x x hhhh high-z write cycle, suspend burst current x x x h h h l x d write cycle, suspend burst current h x x x h h l x d notes: 1. all inputs except oe must meet setup and hold times for the low-to-high transition of clock (clk). 2. wait states are inserted by suspending burst. 3. x means don't care. write =l means any one or more byte write enable signals ( bw 1- bw 4) and bwe are low or gw is low. write =h means all byte write enable signals are high. 4. for a write operation following a read operation, oe must be high before the input data required setup time and held high throughout the input data hold time. 5. adsp low always initiates an internal read at the low-to-high edge of clock. a write is performed by setting one or more byte write enable signals and bwe low or gw low for the subsequent l-h edge of clock. partial truth table function gw gw gw gw gw bwe bwe bwe bwe bwe bw1 bw1 bw1 bw1 bw1 bw2 bw2 bw2 bw2 bw2 bw3 bw3 bw3 bw3 bw3 bw4 bw4 bw4 bw4 bw4 read h h x x x x read h x h h h h write byte 1 h l l h h h write all bytes x lllll write all bytes l xxxxx
is61lv6432 integrated silicon solution, inc. 5 preliminary sr018-1c 06/01/98 issi interleaved burst address table (mode = v ccq or no connect) external address 1st burst address 2nd burst address 3rd burst address a1 a0 a1 a0 a1 a0 a1 a0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 linear burst address table (mode = gnd q ) 0,0 1,0 0,1 a1', a0' = 1,1 absolute maximum ratings (1) symbol parameter value unit t bias temperature under bias C10 to +85 c t stg storage temperature C55 to +150 c p d power dissipation 1.8 w i out output current (per i/o) 100 ma v in , v out voltage relative to gnd for i/o pins C0.5 to v ccq + 0.3 v v in voltage relative to gnd for C0.5 to 4.6 v for address and control inputs notes: 1. stress greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. this device contains circuity to protect the inputs against damage due to high static voltages or electric fields; however, precautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. 3. this device contains circuitry that will ensure the output devices are in high-z at power up.
is61lv6432 6 integrated silicon solution, inc. preliminary sr018-1c 06/01/98 issi operating range range ambient temperature v cc v ccq commercial 0 c to +70 c 3.3v +10%, C5% 2.375v min., 3.465 max. industrial C40 c to +85 c 3.3v +10%, C5% 2.375v min, 3.465v max. dc electrical characteristics (1) (over operating range) symbol parameter test conditions min. max. unit v oh output high voltage i oh = C1.0 ma 2.0 v v ol output low voltage i ol = 1.0 ma 0.4 v v ih input high voltage 1.7 v ccq + 0.3 v v il input low voltage C0.3 0.7 v i li input leakage current gnd v in v ccq (2) com. C5 5 m a ind. C10 10 i lo output leakage current gnd v out v ccq , oe = v ih com. C5 5 m a ind. C10 10 power supply characteristics (operating range) -166 -133 -117 -5 -6 -7 -8 symbol parameter test conditions min. max. min. max. min. max. min. max. min. max. min. max. min. max. unit i cc ac operating device selected, com. 215 205 195 175 165 150 140 ma supply current all inputs = v il or v ih ind. 205 185 175 160 150 oe = v ih , cycle time 3 t kc min. i sb standby current device deselected, com. 70 60 50 25 25 25 25 ma v cc = max., ind. 60 35 35 35 35 clk cycle time 3 t kc min. i zz power-down mode zz = v ccq , com.5555555ma clk running ind. 10 10 10 10 10 current all inputs gnd + 0.2v or 3 v cc C 0.2v note: 1. mode pin have an internal pullup. zz pin has an internal pull-down. these pins may be a no connect, tied to gnd, or tied to v ccq . 2. mode pin should be tied to vcc or gnd. they exhibit 30 m a maximum leakage current when tied to gnd + 0.2v or 3 vcc C 0.2v.
is61lv6432 integrated silicon solution, inc. 7 preliminary sr018-1c 06/01/98 issi capacitance (1,2) symbol parameter conditions max. unit c in input capacitance v in = 0v 6 pf c out input/output capacitance v out = 0v 8 pf notes: 1. tested initially and after any design or process changes that may affect these parameters. 2. test conditions: t a = 25 c, f = 1 mhz, vcc = 3.3v. ac test conditions parameter unit input pulse level for input pins 0v to 3.0v input pulse level for i/o pins 0v to 2.5v input rise and fall times 1.5 ns input and output timing 1.25v and reference level output load see figures 1 and 2 ac test loads figure 1 output buffer z o = 50 w 1.25v 50 w 30 pf figure 2 317 w 5 pf including jig and scope 351 w output 2.5v
is61lv6432 8 integrated silicon solution, inc. preliminary sr018-1c 06/01/98 issi read cycle switching characteristics (over operating range) -166 -133 -117 -5 -6 -7 -8 symbol parameter min. max. min. max. min. max min. max. min. max. min. max. min. max. unit t kc cycle time 6 7.5 8.5 10 12 13 15 ns t kh clock high time 2.4 2.8 3.0 3.5 4 6 6 ns t kl clock low time 2.4 2.8 3.0 3.5 4 6 6 ns t kq clock access time 5 5 5 5 6 7 8 ns t kqx (2) clock high to output invalid 1.5 1.5 1.5 1.5 1.5 2 2 ns t kqlz (2,3) clock high to output low-z 0 0 0 0 0 0 0 ns t kqhz (2,3) clock high to output high-z 1.5 5 1.5 5 1.5 6 1.5 6 1.5 6 2 6 2 6 ns t oeq output enable to output valid 5 5 5 5 6 6 6 ns t oeqx (2) output disable to output invalid 0 0 0 0 0 0 0 ns t oelz (2,3) output enable to output low-z 0 0 0 0 0 0 0 ns t oehz (2,3) output disable to output high-z 3 3 4 4 5 6 6 ns t as address setup time 2.5 2.5 2.5 2.5 2.5 2.5 2.5 ns t ss address status setup time 2.5 2.5 2.5 2.5 2.5 2.5 2.5 ns t ws write setup time 2.5 2.5 2.5 2.5 2.5 2.5 2.5 ns t ces chip enable setup time 2.5 2.5 2.5 2.5 2.5 2.5 2.5 ns t avs address advance setup time 2.5 2.5 2.5 2.5 2.5 2.5 2.5 ns t ah address hold time 0.5 0.5 0.5 0.5 0.5 0.5 0.5 ns t sh address status hold time 0.5 0.5 0.5 0.5 0.5 0.5 0.5 ns t wh write hold time 0.5 0.5 0.5 0.5 0.5 0.5 0.5 ns t ceh chip enable hold time 0.5 0.5 0.5 0.5 0.5 0.5 0.5 ns t avh address advance hold time 0.5 0.5 0.5 0.5 0.5 0.5 0.5 ns t cfg configuration setup (1) 25 30 35 35 45 66.7 80 ns notes: 1. configuration signal mode is static and must not change during normal operation. 2. guaranteed but not 100% tested. this parameter is periodically sampled. 3. tested with load in figure 2.
is61lv6432 integrated silicon solution, inc. 9 preliminary sr018-1c 06/01/98 issi read cycle timing: pipeline single read high-z high-z data out data in oe ce3 ce2 ce1 bw4-bw1 bwe gw a15-a0 adv adsc adsp clk rd1 rd2 1a 2c 2d 3a unselected burst read t kqx t kc t kl t kh t ss t sh t ss t sh t as t ah t ws t wh t ws t wh rd3 t ces t ceh t ces t ceh t ces t ceh ce2 and ce3 only sampled with adsp or adsc ce1 masks adsp unselected with ce2 t oeq t oeqx t oelz t kqlz t kq t oehz t kqhz adsc initiate read adsp is blocked by ce1 inactive t avh t avs suspend burst pipelined read 2a 2b
is61lv6432 10 integrated silicon solution, inc. preliminary sr018-1c 06/01/98 issi write cycle switching characteristics (over operating range) -166 -133 -117 -5 -6 -7 -8 symbol parameter min. max. min. max. min. max. min. max. min. max. min. max. min. max. unit t kc cycle time 6 7.5 8.5 10 12 13 15 ns t kh clock high time 2.4 2.8 3.0 3.5 4 6 6 ns t kl clock low time 2.4 2.8 3.0 3.5 4 6 6 ns t as address setup time 2.5 2.5 2.5 2.5 2.5 2.5 2.5 ns t ss address status setup time 2.5 2.5 2.5 2.5 2.5 2.5 2.5 ns t ws write setup time 2.5 2.5 2.5 2.5 2.5 2.5 2.5 ns t ds data in setup time 2.5 2.5 2.5 2.5 2.5 2.5 2.5 ns t ces chip enable setup time 2.5 2.5 2.5 2.5 2.5 2.5 2.5 ns t avs address advance setup time 2.5 2.5 2.5 2.5 2.5 2.5 2.5 ns t ah address hold time 0.5 0.5 0.5 0.5 0.5 0.5 0.5 ns t sh address status hold time 0.5 0.5 0.5 0.5 0.5 0.5 0.5 ns t dh data in hold time 0.5 0.5 0.5 0.5 0.5 0.5 0.5 ns t wh write hold time 0.5 0.5 0.5 0.5 0.5 0.5 0.5 ns t ceh chip enable hold time 0.5 0.5 0.5 0.5 0.5 0.5 0.5 ns t avh address advance hold time 0.5 0.5 0.5 0.5 0.5 0.5 0.5 ns t cfg configuration setup (1) 25 30 35 35 45 52 60 ns notes: 1. configuration signal mode is static and must not change during normal operation.
is61lv6432 integrated silicon solution, inc. 11 preliminary sr018-1c 06/01/98 issi write cycle timing single write data out data in oe ce3 ce2 ce1 bw4-bw1 bwe gw a15-a0 adv adsc adsp clk wr1 wr2 unselected burst write t kc t kl t kh t ss t sh t as t ah t ws t wh t ws t wh wr3 t ces t ceh t ces t ceh t ces t ceh ce2 and ce3 only sampled with adsp or adsc ce1 masks adsp unselected with ce2 adsc initiate write adsp is blocked by ce1 inactive t avh t avs adv must be inactive for adsp write wr1 wr2 t ws t wh wr3 t ws t wh high-z high-z 1a 3a t ds t dh bw4-bw1 only are applied to first cycle of wr2 write 2c 2d 2b 2a
is61lv6432 12 integrated silicon solution, inc. preliminary sr018-1c 06/01/98 issi read/write cycle switching characteristics (over operating range) -166 -133 -117 -5 -6 -7 -8 symbol parameter min. max. min. max. min. max. min. max. min. max. min. max. min. max. unit t kc cycle time 6 7.5 8.5 10 12 13 15 ns t kh clock high time 2.4 2.8 3.0 3.5 4 6 6 ns t kl clock low time 2.4 2.8 3.0 3.5 4 6 6 ns t kq clock access time 5 5 5 5 6 7 8 ns t kqx (2) clock high to output invalid 1.5 1.5 1.5 1.5 1.5 2 2 ns t kqlz (2,3) clock high to output low-z 0 0 0 0 0 0 0 ns t kqhz (2,3) clock high to output high-z 1.5 5 1.5 5 1.5 6 1.5 6 1.5 6 2 6 2 6 ns t oeq output enable to output valid 5 5 5 5 6 6 6 ns t oeqx (2) output disable to output invalid 0 0 0 0 0 0 0 ns t oelz (2,3) output enable to output low-z 0 0 0 0 0 0 0 ns t oehz (2,3) output disable to output high-z 3 3 4 4 5 6 6 ns t as address setup time 2.5 2.5 2.5 2.5 2.5 2.5 2.5 ns t ss address status setup time 2.5 2.5 2.5 2.5 2.5 2.5 2.5 ns t ws write setup time 2.5 2.5 2.5 2.5 2.5 2.5 2.5 ns t ces chip enable setup time 2.5 2.5 2.5 2.5 2.5 2.5 2.5 ns t ah address hold time 0.5 0.5 0.5 0.5 0.5 0.5 0.5 ns t sh address status hold time 0.5 0.5 0.5 0.5 0.5 0.5 0.5 ns t wh write hold time 0.5 0.5 0.5 0.5 0.5 0.5 0.5 ns t ceh chip enable hold time 0.5 0.5 0.5 0.5 0.5 0.5 0.5 ns t cfg configuration setup (1) 2.5 30 35 35 45 52 60 ns notes: 1. configuration signal mode is static and must not change during normal operation. 2. guaranteed but not 100% tested. this parameter is periodically sampled. 3. tested with load in figure 2.
is61lv6432 integrated silicon solution, inc. 13 preliminary sr018-1c 06/01/98 issi read/write cycle timing: pipeline single read single write high-z high-z data out data in oe ce3 ce2 ce1 bw4-bw1 bwe gw a15-a0 adv adsc adsp clk rd1 wr1 wr1 1a 1a 2a 2b 2c 2d unselected burst read t kqx t kc t kl t kh t ss t sh adsp is blocked by ce1 inactive t ss t sh t as t ah t ws t wh t ws t wh t ws t wh rd2 rd3 t ces t ceh t ces t ceh t ces t ceh ce2 and ce3 only sampled with adsp or adsc ce1 masks adsp unselected with ce3 t oeq t oeqx t oelz t kqlz t kq t oehz t kqx t kqhz t ds t dh t kqhz
is61lv6432 14 integrated silicon solution, inc. preliminary sr018-1c 06/01/98 issi snooze and recovery cycle switching characteristics (over operating range) -166 -133 -117 -5 -6 -7 -8 symbol parameter min. max min. max. min. max. min. max. min. max. min. max. min. max. unit t kc cycle time 6 7.5 8.5 10 12 13 15 ns t kh clock high time 2.4 2.8 3.0 3.5 4 6 6 ns t kl clock low time 2.4 2.8 3.0 3.5 4 6 6 ns t kq clock access time 5 5 5 5 6 7 8 ns t kqx (4) clock high to output invalid 1.5 1.5 1.5 1.5 1.5 2 2 ns t kqlz (4,5) clock high to output low-z 0 0 0 0 0 0 0 ns t kqhz (4,5) clock high to output high-z 1.5 5 1.5 5 1.5 6 1.5 6 1.5 6 2 6 2 6 ns t oeq output enable to output valid 5 5 5 5 6 6 6 ns t oeqx (4) output disable to output invalid 0 0 0 0 0 0 0 ns t oelz (4,5) output enable to output low-z 0 0 0 0 0 0 0 ns t oehz (4,5) output disable to output high-z 3 3 4 4 5 6 6 ns t as address setup time 2.5 2.5 2.5 2.5 2.5 2.5 2.5 ns t ss address status setup time 2.5 2.5 2.5 2.5 2.5 2.5 2.5 ns t ces chip enable setup time 2.5 2.5 2.5 2.5 2.5 2.5 2.5 ns t ah address hold time 2.5 2.5 2.5 2.5 2.5 2.5 2.5 ns t sh address status hold time 2.5 2.5 2.5 2.5 2.5 2.5 2.5 ns t ceh chip enable hold time 2.5 2.5 2.5 2.5 2.5 2.5 2.5 ns t zzs zz standby (1) 2 2 2 2 2 2 2 cyc t zzrec zz recovery (2) 2 2 2 2 2 2 2 cyc notes: 1. the assertion of zz allows the sram to enter a lower power state than when deselected within the time specified. data retention is guaranteed when zz is asserted and clock remains active. 2. adsc and adsp must not be asserted for at least 2 cyc after leaving zz state. 3. configuration signal mode is static and must not change during normal operation. 4. guaranteed but not 100% tested. this parameter is periodically sampled. 5. tested with load in figure 2.
is61lv6432 integrated silicon solution, inc. 15 preliminary sr018-1c 06/01/98 issi snooze and recovery cycle timing single read high-z high-z data out data in oe ce3 ce2 ce1 bw4-bw1 bwe gw a15-a0 adv adsc adsp clk rd1 1a read snooze with data retention t kc t kl t kh t ss t sh t as t ah rd2 t ces t ceh t ces t ceh t ces t ceh t oeq t oeqx t oelz t kqlz t kq t oehz t kqx t kqhz zz t zzs t zzrec
is61lv6432 16 integrated silicon solution, inc. preliminary sr018-1c 06/01/98 issi ordering information commercial range: 0 c to +70 c frequency (mhz) order part number package 166 is61lv6432-166tq tqfp is61lv6432-166pq pqfp 133 is61lv6432-133tq tqfp is61lv6432-133pq pqfp 117 is61lv6432-117tq tqfp is61lv6432-117pq pqfp 100 is61lv6432-5tq tqfp is61lv6432-5pq pqfp 83 is61lv6432-6tq tqfp IS61LV6432-6PQ pqfp 75 is61lv6432-7tq tqfp is61lv6432-7pq pqfp 66 is61lv6432-8tq tqfp is61lv6432-8pq pqfp notice integrated silicon solution, inc., reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. integrated silicon solution, inc. assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. charts and schedules contained herein reflect representative operating parameters, and may vary depending upon a user's specific application. while the information in this publication has been carefully checked, integrated silicon solution, inc. shall not be liable for any damages arising as a result of any error or omission. integrated silicon solution, inc. does not recommend the use of any of its products in life support applications where the fail ure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. products are not authorized for use in such applications unless integrated silicon solution, inc. receives written assurances, to its satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assum es all such risks; and (c) potential liability of integrated silicon solution, inc. is adequately protected under the circumstance s. copyright 1998 integrated silicon solution, inc. reproduction in whole or in part, without the prior written consent of integrated silicon solution, inc., is prohibited. integrated silicon solution, inc. 2231 lawson lane santa clara, ca 95054 tel: 1-800-379-4774 fax: (408) 588-0806 e-mail: sales@issi.com http://www.issi.com ordering information industrial range: C40 c to +85 c frequency (mhz) order part number package 117 is61lv6432-117tqi tqfp is61lv6432-117pqi pqfp 100 is61lv6432-5tqi tqfp is61lv6432-5pqi pqfp 83 is61lv6432-6tqi tqfp IS61LV6432-6PQi pqfp 75 is61lv6432-7tqi tqfp is61lv6432-7pqi pqfp 66 is61lv6432-8tqi tqfp is61lv6432-8pqi pqfp issi

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